A NAND flash memory is known as an electrically rewritable and highly integratable non-volatile memory device. The NAND flash memory includes a NAND cell unit. The NAND cell unit includes a plurality of memory cells connected in series. The adjacent memory cells share a source/drain diffusion layer. The NAND cell unit has ends connected to a bit-line and a source-line via select gate transistors, respectively. This NAND cell unit configuration can provide a smaller unit cell area and a larger mass storage than the NOR flash memory.
The memory cells of the NAND flash memory each include a semiconductor substrate, a charge accumulation layer (a floating gate electrode) formed on the substrate via a tunnel insulating film, a control gate electrode stacked on the charge accumulation layer via an inter-gate dielectric film. Each memory cell stores data in a non-volatile manner using the charge accumulation state of the floating gate electrode. For example, the binary data storage is performed by setting data “0” as a high threshold voltage state in which electrons are injected into the floating gate electrode and data “1” as a low threshold voltage state in which electrons are discharged from the floating gate electrode. The threshold voltage distribution to be written has recently been divided to provide a multi-level storage such as a four-level or eight-level storage.
Recently, as the minimum processing dimension has become ever smaller and the non-volatile memory device has become more compact, the distance between the word-lines, or between the word-line and the select gate line has become smaller. Smaller distance between the word-lines means that a word-line leak occurs more likely. Therefore, the generation of the word-line leak needs to be checked, and there is a need for a proposed non-volatile semiconductor memory device that can quickly and reliably detect the generation location of the word-line leak.
Unfortunately, in a conventional non-volatile semiconductor memory device, it is necessary to provide, on a chip, a pad and a switch dedicated to the detection of the word-line leak, which is obstacle to the smaller chip area. It is also necessary to detect the word-line leak for each word-line or each block, resulting in the issue of a longer check time.